AN1151: Using the Si539x in 56G SerDes Applications Ethernet speeds are continuing to increase, pushing to 400G and beyond due to demands for more data delivered at faster speeds. The latest switch processor chips with 56G PAM-4 interfaces have allowed for new high-speed interconnects in the cloud and data center networks. MILPITAS, CA- May 08, 2017- Credo Semiconductor, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced a comprehensive portfolio of 56G and 112G PAM-4 PHY devices, enabling connectivity for enterprise, hyperscale datacenter, and service provider networks.
Configurability of industry’s lowest-area, lowest-power core provided optimal solution for eSilicon
SAN MATEO, Calif. and SAN JOSE, Calif. – Aug. 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after extensive review and testing of available options in the market, eSilicon has selected the SiFive E2 Core IP Series as the best solution for its next-generation SerDes IP at 7nm.
eSilicon’s 7nm SerDes IP represents a new breed of performance and versatility based on a novel DSP-based architecture. Two 7nm PHYs support 56G and 112G NRZ/PAM4 operation to provide the best power efficiency tradeoffs for server, fabric and line-card applications. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane.
“Today’s high-performance networking applications require the ability to balance power and density to effectively address increasing performance demands,” said Hugh Durdan, vice president of strategy and products at eSilicon. “SiFive’s E2 Core IP allows eSilicon to provide the flexibility and configurability that our customers require while achieving industry-leading power, performance, and area.”
The SiFive E2 Core IP is designed for markets that require extremely low-cost, low-power computing, but can benefit from being fully integrated within the RISC-V software ecosystem. At one-third the area and one-third the power consumption of similar competitor cores, the SiFive E2 Core series is the natural selection for companies like eSilicon that are looking to address the challenges of advanced ASIC designs.
“eSilicon has a successful track record for leveraging the most advanced technologies to develop high-bandwidth, power-efficient IP for ASIC design,” said Brad Holtzinger, vice president of sales, SiFive. “Our E2 Core Series IP takes advantage of the inherent scalability of RISC-V to bring the highest performance possible to the demands of advanced ASICs. We look forward to working with eSilicon on its next-generation SerDes to address these demands.”
About SiFive
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Huami, SK Telecom, Western Digital and Intel Capital. For more information, visit www.sifive.com.
About eSilicon
eSilicon is an independent provider of complex FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 16/14/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com
Contact:
Leslie Clavin
SHIFT Communications for SiFive
(415) 591-8440
[email protected]
Sally Slemons
eSilicon Corporation
(408) 635-6409
[email protected]
Enabling Next-Generation Servers, Switches, Routers and 5G Infrastructure
Networking systems are becoming increasingly complex. Meeting the power, performance and density requirements of advanced networking-class ASICs is a significant challenge for system OEMs. Next-generation 12.8, 25.6 and 51.2Tb/s switches and routers demand extreme flexibility in system architecture, greater I/O bandwidth and power scaling to achieve the required performance and density.
Key challenges facing network architects are:
- The number of SerDes lanes is approaching 300
- System power is exploding, sometimes reaching over 400W
- Legacy backplanes have high insertion loss, limiting the maximum throughput
The SerDes family is a critical piece of eSilicon’s 7nm IP platform that provides a complete ecosystem of networking-optimized, highly configurable IP. All of the IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility results in better performance, higher density and faster time to market.
At the core of the 7nm IP platform is eSilicon’s SerDes technology which delivers a new level of performance and versatility and is based on a novel DSP-based architecture. Two 7nm PHYs support 56G and 112G NRZ/PAM4 operation to provide the best power efficiency for server, switches and routers. The architecture delivers unprecedented power efficiency for a true long-reach capability, with hole-free operation down to 1Gb/s. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane. A multitude of protocols are supported including a variety of Ethernet standards and Fibre Channel. The architecture also allows further reductions in power consumption for shorter-reach channels.
Enabling Next-Gen 25.6 and 51.2Tb/s Switches, Routers and 800G Systems
Unique Benefits of eSilicon’s 7nm 56G/112G SerDes Family
- Unprecedented power efficiency for 56G and 112G applications
- Optimized form factor for networking applications
- Programmable to enable the best power and reach trade-offs for a given application
- First-to-market full DSP (Tx and Rx) 56G SerDes in 7nm with true long-reach performancefor use in the most challenging backplane applications
- Maximum clocking flexibility – hole-free down to 1Gb/s
- Long and short channel support
- Design flexibility through a unique clocking architecture and firmware-controlled design
- User-centric experience for greater ease of use, bring-up and validation
Features
- Reduce time to market with our revolutionary graphical user interface (GUI) that allows quick, easy bring-up and system validation. From the GUI, users can access all the monitoring features such as non-destructive eye diagrams, SNR & BER, bathtubs, histograms and power measurements
- Microprocessor-enabled link monitoring including channel impulse response and error histogram
- Self-calibrated architecture with optimized power/performance trade-offs
- Multiple operational modes to support reference and reference-less applications
- Wide variety of IEEE and OIF-standardized protocols including Ethernet and Fibre Channel
ASIC & SerDes Expertise
Our new SerDes family was developed by a world-class SerDes team with over 12 years of proven experience in networking, including two 28nm silicon-proven 56G SerDes implementations. The new SerDes family leverages the same architecture plus some unique features derived from eSilicon’s long-standing experience integrating complex SerDes into bleeding-edge networking ASICs.
In addition to outstanding performance and versatility, eSilicon’s SerDes family provides a new level of user experience for the ASIC design and signal integrity communities. Leveraging a decade of experience integrating complex SerDes into networking ASICs, eSilicon incorporated this unique knowledge into its new 7nm SerDes family. The result is a new-to-the-market, customer-centric SerDes that is easy to integrate and easy to use.
Reach Beyond the Rack
Our true long-reach DSP-based SerDes coupled with Samtec’s low-loss Twinax Flyover Cable Assembly enables reach beyond the rack: five meters and beyond for data centers and 5G wireless infrastructure, an industry first.
Detailed Information
Additional features and benefits for eSilicon’s SerDes family and the rest of the 7nm IP platform are available under NDA.
You can schedule a demonstration of the 56G SerDes test chip by contacting your eSilicon sales representative directly or via [email protected]. Demo boards are also available for customer evaluation via [email protected].